commit 3dfe8ceffa7d6fb528f92ec31deddb73579102d1
author commit-queue@webkit.org <commit-queue@webkit.org@268f45cc-cd09-0410-ab3c-d52691b4dbfc> Tue Aug 07 22:55:04 2012 +0000
committer commit-queue@webkit.org <commit-queue@webkit.org@268f45cc-cd09-0410-ab3c-d52691b4dbfc> Tue Aug 07 22:55:04 2012 +0000
tree 88a630251f66b852f2444db400fc0eb7b15582be
parent 3daa0ce07cb5fc6f3f1c73045b73500c12b2f074

Refactor magic numbers in the ARM port of DFG-JIT
https://bugs.webkit.org/show_bug.cgi?id=93348

Patch by Gabor Ballabas <gaborb@inf.u-szeged.hu> on 2012-08-07
Reviewed by Eric Seidel.

Introduce new names for hard-coded magic numbers.
Refactor constant with confusing names to more descriptive ones.

* assembler/ARMAssembler.cpp:
(JSC::ARMAssembler::patchConstantPoolLoad):
(JSC::ARMAssembler::getOp2):
(JSC::ARMAssembler::genInt):
(JSC::ARMAssembler::getImm):
(JSC::ARMAssembler::moveImm):
(JSC::ARMAssembler::encodeComplexImm):
(JSC::ARMAssembler::dataTransfer32):
(JSC::ARMAssembler::dataTransfer16):
(JSC::ARMAssembler::dataTransferFloat):
(JSC::ARMAssembler::executableCopy):
* assembler/ARMAssembler.h:
(JSC::ARMAssembler::emitInstruction):
(JSC::ARMAssembler::ands_r):
(JSC::ARMAssembler::eors_r):
(JSC::ARMAssembler::subs_r):
(JSC::ARMAssembler::rsbs_r):
(JSC::ARMAssembler::adds_r):
(JSC::ARMAssembler::adcs_r):
(JSC::ARMAssembler::sbcs_r):
(JSC::ARMAssembler::rscs_r):
(JSC::ARMAssembler::tst_r):
(JSC::ARMAssembler::teq_r):
(JSC::ARMAssembler::cmp_r):
(JSC::ARMAssembler::cmn_r):
(JSC::ARMAssembler::orrs_r):
(JSC::ARMAssembler::movs_r):
(JSC::ARMAssembler::bics_r):
(JSC::ARMAssembler::mvns_r):
(JSC::ARMAssembler::muls_r):
(JSC::ARMAssembler::ldr_imm):
(JSC::ARMAssembler::ldr_un_imm):
(JSC::ARMAssembler::dtr_u):
(JSC::ARMAssembler::dtr_ur):
(JSC::ARMAssembler::dtr_dr):
(JSC::ARMAssembler::dtrh_u):
(JSC::ARMAssembler::dtrh_ur):
(JSC::ARMAssembler::fdtr_u):
(JSC::ARMAssembler::push_r):
(JSC::ARMAssembler::pop_r):
(JSC::ARMAssembler::getLdrImmAddress):
(JSC::ARMAssembler::getLdrImmAddressOnPool):
(JSC::ARMAssembler::patchConstantPoolLoad):
(JSC::ARMAssembler::repatchCompact):
(JSC::ARMAssembler::replaceWithJump):
(JSC::ARMAssembler::replaceWithLoad):
(JSC::ARMAssembler::replaceWithAddressComputation):
(JSC::ARMAssembler::getOp2Byte):
(JSC::ARMAssembler::getOp2Half):
(JSC::ARMAssembler::getImm16Op2):
(JSC::ARMAssembler::placeConstantPoolBarrier):
(JSC::ARMAssembler::getConditionalField):
* assembler/MacroAssemblerARM.cpp:
(JSC::MacroAssemblerARM::load32WithUnalignedHalfWords):
* assembler/MacroAssemblerARM.h:
(JSC::MacroAssemblerARM::and32):
(JSC::MacroAssemblerARM::branch32):
(JSC::MacroAssemblerARM::branchTest32):
(JSC::MacroAssemblerARM::branchTruncateDoubleToInt32):

git-svn-id: http://svn.webkit.org/repository/webkit/trunk@124930 268f45cc-cd09-0410-ab3c-d52691b4dbfc

Source/JavaScriptCore/assembler/MacroAssemblerARM.h

diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerARM.h b/Source/JavaScriptCore/assembler/MacroAssemblerARM.h
index 530f62b..85d0ffb 100644
--- a/Source/JavaScriptCore/assembler/MacroAssemblerARM.h
+++ b/Source/JavaScriptCore/assembler/MacroAssemblerARM.h
@@ -137,8 +137,8 @@
     void and32(TrustedImm32 imm, RegisterID dest)
     {
         ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
-        if (w & ARMAssembler::OP2_INV_IMM)
-            m_assembler.bics_r(dest, dest, w & ~ARMAssembler::OP2_INV_IMM);
+        if (w & ARMAssembler::Op2InvertedImmediate)
+            m_assembler.bics_r(dest, dest, w & ~ARMAssembler::Op2InvertedImmediate);
         else
             m_assembler.ands_r(dest, dest, w);
     }
@@ -146,8 +146,8 @@
     void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)
     {
         ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
-        if (w & ARMAssembler::OP2_INV_IMM)
-            m_assembler.bics_r(dest, src, w & ~ARMAssembler::OP2_INV_IMM);
+        if (w & ARMAssembler::Op2InvertedImmediate)
+            m_assembler.bics_r(dest, src, w & ~ARMAssembler::Op2InvertedImmediate);
         else
             m_assembler.ands_r(dest, src, w);
     }
@@ -555,8 +555,8 @@
 
     Jump branch32(RelationalCondition cond, RegisterID left, TrustedImm32 right, int useConstantPool = 0)
     {
-        ARMWord tmp = (right.m_value == 0x80000000) ? ARMAssembler::INVALID_IMM : m_assembler.getOp2(-right.m_value);
-        if (tmp != ARMAssembler::INVALID_IMM)
+        ARMWord tmp = (right.m_value == 0x80000000) ? ARMAssembler::InvalidImmediate : m_assembler.getOp2(-right.m_value);
+        if (tmp != ARMAssembler::InvalidImmediate)
             m_assembler.cmn_r(left, tmp);
         else
             m_assembler.cmp_r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
@@ -617,8 +617,8 @@
     {
         ASSERT((cond == Zero) || (cond == NonZero));
         ARMWord w = m_assembler.getImm(mask.m_value, ARMRegisters::S0, true);
-        if (w & ARMAssembler::OP2_INV_IMM)
-            m_assembler.bics_r(ARMRegisters::S0, reg, w & ~ARMAssembler::OP2_INV_IMM);
+        if (w & ARMAssembler::Op2InvertedImmediate)
+            m_assembler.bics_r(ARMRegisters::S0, reg, w & ~ARMAssembler::Op2InvertedImmediate);
         else
             m_assembler.tst_r(reg, w);
         return Jump(m_assembler.jmp(ARMCondition(cond)));
@@ -1152,7 +1152,7 @@
         m_assembler.bic_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));
 
         ARMWord w = ARMAssembler::getOp2(0x80000000);
-        ASSERT(w != ARMAssembler::INVALID_IMM);
+        ASSERT(w != ARMAssembler::InvalidImmediate);
         m_assembler.cmp_r(ARMRegisters::S0, w);
         return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE));
     }