Refactor magic numbers in the ARM port of DFG-JIT
https://bugs.webkit.org/show_bug.cgi?id=93348
Patch by Gabor Ballabas <gaborb@inf.u-szeged.hu> on 2012-08-07
Reviewed by Eric Seidel.
Introduce new names for hard-coded magic numbers.
Refactor constant with confusing names to more descriptive ones.
* assembler/ARMAssembler.cpp:
(JSC::ARMAssembler::patchConstantPoolLoad):
(JSC::ARMAssembler::getOp2):
(JSC::ARMAssembler::genInt):
(JSC::ARMAssembler::getImm):
(JSC::ARMAssembler::moveImm):
(JSC::ARMAssembler::encodeComplexImm):
(JSC::ARMAssembler::dataTransfer32):
(JSC::ARMAssembler::dataTransfer16):
(JSC::ARMAssembler::dataTransferFloat):
(JSC::ARMAssembler::executableCopy):
* assembler/ARMAssembler.h:
(JSC::ARMAssembler::emitInstruction):
(JSC::ARMAssembler::ands_r):
(JSC::ARMAssembler::eors_r):
(JSC::ARMAssembler::subs_r):
(JSC::ARMAssembler::rsbs_r):
(JSC::ARMAssembler::adds_r):
(JSC::ARMAssembler::adcs_r):
(JSC::ARMAssembler::sbcs_r):
(JSC::ARMAssembler::rscs_r):
(JSC::ARMAssembler::tst_r):
(JSC::ARMAssembler::teq_r):
(JSC::ARMAssembler::cmp_r):
(JSC::ARMAssembler::cmn_r):
(JSC::ARMAssembler::orrs_r):
(JSC::ARMAssembler::movs_r):
(JSC::ARMAssembler::bics_r):
(JSC::ARMAssembler::mvns_r):
(JSC::ARMAssembler::muls_r):
(JSC::ARMAssembler::ldr_imm):
(JSC::ARMAssembler::ldr_un_imm):
(JSC::ARMAssembler::dtr_u):
(JSC::ARMAssembler::dtr_ur):
(JSC::ARMAssembler::dtr_dr):
(JSC::ARMAssembler::dtrh_u):
(JSC::ARMAssembler::dtrh_ur):
(JSC::ARMAssembler::fdtr_u):
(JSC::ARMAssembler::push_r):
(JSC::ARMAssembler::pop_r):
(JSC::ARMAssembler::getLdrImmAddress):
(JSC::ARMAssembler::getLdrImmAddressOnPool):
(JSC::ARMAssembler::patchConstantPoolLoad):
(JSC::ARMAssembler::repatchCompact):
(JSC::ARMAssembler::replaceWithJump):
(JSC::ARMAssembler::replaceWithLoad):
(JSC::ARMAssembler::replaceWithAddressComputation):
(JSC::ARMAssembler::getOp2Byte):
(JSC::ARMAssembler::getOp2Half):
(JSC::ARMAssembler::getImm16Op2):
(JSC::ARMAssembler::placeConstantPoolBarrier):
(JSC::ARMAssembler::getConditionalField):
* assembler/MacroAssemblerARM.cpp:
(JSC::MacroAssemblerARM::load32WithUnalignedHalfWords):
* assembler/MacroAssemblerARM.h:
(JSC::MacroAssemblerARM::and32):
(JSC::MacroAssemblerARM::branch32):
(JSC::MacroAssemblerARM::branchTest32):
(JSC::MacroAssemblerARM::branchTruncateDoubleToInt32):
git-svn-id: http://svn.webkit.org/repository/webkit/trunk@124930 268f45cc-cd09-0410-ab3c-d52691b4dbfc
diff --git a/Source/JavaScriptCore/assembler/ARMAssembler.h b/Source/JavaScriptCore/assembler/ARMAssembler.h
index 962724f..ac918f3 100644
--- a/Source/JavaScriptCore/assembler/ARMAssembler.h
+++ b/Source/JavaScriptCore/assembler/ARMAssembler.h
@@ -179,52 +179,50 @@
};
enum {
- OP2_IMM = (1 << 25),
- OP2_IMM_HALF = (1 << 22),
- OP2_INV_IMM = (1 << 26),
- SET_CC = (1 << 20),
- OP2_OFSREG = (1 << 25),
+ Op2Immediate = (1 << 25),
+ ImmediateForHalfWordTransfer = (1 << 22),
+ Op2InvertedImmediate = (1 << 26),
+ SetConditionalCodes = (1 << 20),
+ Op2IsRegisterArgument = (1 << 25),
// Data transfer flags.
- DT_UP = (1 << 23),
- DT_WB = (1 << 21),
- DT_PRE = (1 << 24),
- DT_LOAD = (1 << 20),
- DT_BYTE = (1 << 22),
+ DataTransferUp = (1 << 23),
+ DataTransferWriteBack = (1 << 21),
+ DataTransferPostUpdate = (1 << 24),
+ DataTransferLoad = (1 << 20),
+ ByteDataTransfer = (1 << 22),
};
enum DataTransferTypeA {
- LoadUint32 = 0x05000000 | DT_LOAD,
- LoadUint8 = 0x05400000 | DT_LOAD,
+ LoadUint32 = 0x05000000 | DataTransferLoad,
+ LoadUint8 = 0x05400000 | DataTransferLoad,
StoreUint32 = 0x05000000,
StoreUint8 = 0x05400000,
};
enum DataTransferTypeB {
- LoadUint16 = 0x010000b0 | DT_LOAD,
- LoadInt16 = 0x010000f0 | DT_LOAD,
- LoadInt8 = 0x010000d0 | DT_LOAD,
+ LoadUint16 = 0x010000b0 | DataTransferLoad,
+ LoadInt16 = 0x010000f0 | DataTransferLoad,
+ LoadInt8 = 0x010000d0 | DataTransferLoad,
StoreUint16 = 0x010000b0,
};
enum DataTransferTypeFloat {
- LoadFloat = 0x0d000a00 | DT_LOAD,
- LoadDouble = 0x0d000b00 | DT_LOAD,
+ LoadFloat = 0x0d000a00 | DataTransferLoad,
+ LoadDouble = 0x0d000b00 | DataTransferLoad,
StoreFloat = 0x0d000a00,
StoreDouble = 0x0d000b00,
};
// Masks of ARM instructions
enum {
- BRANCH_MASK = 0x00ffffff,
- NONARM = 0xf0000000,
- SDT_MASK = 0x0c000000,
- SDT_OFFSET_MASK = 0xfff,
+ BranchOffsetMask = 0x00ffffff,
+ ConditionalFieldMask = 0xf0000000,
+ DataTransferOffsetMask = 0xfff,
};
enum {
- BOFFSET_MIN = -0x00800000,
- BOFFSET_MAX = 0x007fffff,
- SDT = 0x04000000,
+ MinimumBranchOffsetDistance = -0x00800000,
+ MaximumBranchOffsetDistance = 0x007fffff,
};
enum {
@@ -233,15 +231,24 @@
padForAlign32 = 0xe12fff7f // 'bkpt 0xffff' instruction.
};
- static const ARMWord INVALID_IMM = 0xf0000000;
+ static const ARMWord InvalidImmediate = 0xf0000000;
static const ARMWord InvalidBranchTarget = 0xffffffff;
- static const int DefaultPrefetching = 2;
+ static const int DefaultPrefetchOffset = 2;
+
+ static const ARMWord BlxInstructionMask = 0x012fff30;
+ static const ARMWord LdrOrAddInstructionMask = 0x0ff00000;
+ static const ARMWord LdrPcImmediateInstructionMask = 0x0f7f0000;
+
+ static const ARMWord AddImmediateInstruction = 0x02800000;
+ static const ARMWord BlxInstruction = 0x012fff30;
+ static const ARMWord LdrImmediateInstruction = 0x05900000;
+ static const ARMWord LdrPcImmediateInstruction = 0x051f0000;
// Instruction formating
void emitInstruction(ARMWord op, int rd, int rn, ARMWord op2)
{
- ASSERT(((op2 & ~OP2_IMM) <= 0xfff) || (((op2 & ~OP2_IMM_HALF) <= 0xfff)));
+ ASSERT(((op2 & ~Op2Immediate) <= 0xfff) || (((op2 & ~ImmediateForHalfWordTransfer) <= 0xfff)));
m_buffer.putInt(op | RN(rn) | RD(rd) | op2);
}
@@ -268,7 +275,7 @@
void ands_r(int rd, int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | AND | SET_CC, rd, rn, op2);
+ emitInstruction(toARMWord(cc) | AND | SetConditionalCodes, rd, rn, op2);
}
void eor_r(int rd, int rn, ARMWord op2, Condition cc = AL)
@@ -278,7 +285,7 @@
void eors_r(int rd, int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | EOR | SET_CC, rd, rn, op2);
+ emitInstruction(toARMWord(cc) | EOR | SetConditionalCodes, rd, rn, op2);
}
void sub_r(int rd, int rn, ARMWord op2, Condition cc = AL)
@@ -288,7 +295,7 @@
void subs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | SUB | SET_CC, rd, rn, op2);
+ emitInstruction(toARMWord(cc) | SUB | SetConditionalCodes, rd, rn, op2);
}
void rsb_r(int rd, int rn, ARMWord op2, Condition cc = AL)
@@ -298,7 +305,7 @@
void rsbs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | RSB | SET_CC, rd, rn, op2);
+ emitInstruction(toARMWord(cc) | RSB | SetConditionalCodes, rd, rn, op2);
}
void add_r(int rd, int rn, ARMWord op2, Condition cc = AL)
@@ -308,7 +315,7 @@
void adds_r(int rd, int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | ADD | SET_CC, rd, rn, op2);
+ emitInstruction(toARMWord(cc) | ADD | SetConditionalCodes, rd, rn, op2);
}
void adc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
@@ -318,7 +325,7 @@
void adcs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | ADC | SET_CC, rd, rn, op2);
+ emitInstruction(toARMWord(cc) | ADC | SetConditionalCodes, rd, rn, op2);
}
void sbc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
@@ -328,7 +335,7 @@
void sbcs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | SBC | SET_CC, rd, rn, op2);
+ emitInstruction(toARMWord(cc) | SBC | SetConditionalCodes, rd, rn, op2);
}
void rsc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
@@ -338,27 +345,27 @@
void rscs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | RSC | SET_CC, rd, rn, op2);
+ emitInstruction(toARMWord(cc) | RSC | SetConditionalCodes, rd, rn, op2);
}
void tst_r(int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | TST | SET_CC, 0, rn, op2);
+ emitInstruction(toARMWord(cc) | TST | SetConditionalCodes, 0, rn, op2);
}
void teq_r(int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | TEQ | SET_CC, 0, rn, op2);
+ emitInstruction(toARMWord(cc) | TEQ | SetConditionalCodes, 0, rn, op2);
}
void cmp_r(int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | CMP | SET_CC, 0, rn, op2);
+ emitInstruction(toARMWord(cc) | CMP | SetConditionalCodes, 0, rn, op2);
}
void cmn_r(int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | CMN | SET_CC, 0, rn, op2);
+ emitInstruction(toARMWord(cc) | CMN | SetConditionalCodes, 0, rn, op2);
}
void orr_r(int rd, int rn, ARMWord op2, Condition cc = AL)
@@ -368,7 +375,7 @@
void orrs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | ORR | SET_CC, rd, rn, op2);
+ emitInstruction(toARMWord(cc) | ORR | SetConditionalCodes, rd, rn, op2);
}
void mov_r(int rd, ARMWord op2, Condition cc = AL)
@@ -392,7 +399,7 @@
void movs_r(int rd, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | MOV | SET_CC, rd, ARMRegisters::r0, op2);
+ emitInstruction(toARMWord(cc) | MOV | SetConditionalCodes, rd, ARMRegisters::r0, op2);
}
void bic_r(int rd, int rn, ARMWord op2, Condition cc = AL)
@@ -402,7 +409,7 @@
void bics_r(int rd, int rn, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | BIC | SET_CC, rd, rn, op2);
+ emitInstruction(toARMWord(cc) | BIC | SetConditionalCodes, rd, rn, op2);
}
void mvn_r(int rd, ARMWord op2, Condition cc = AL)
@@ -412,7 +419,7 @@
void mvns_r(int rd, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | MVN | SET_CC, rd, ARMRegisters::r0, op2);
+ emitInstruction(toARMWord(cc) | MVN | SetConditionalCodes, rd, ARMRegisters::r0, op2);
}
void mul_r(int rd, int rn, int rm, Condition cc = AL)
@@ -422,7 +429,7 @@
void muls_r(int rd, int rn, int rm, Condition cc = AL)
{
- m_buffer.putInt(toARMWord(cc) | MUL | SET_CC | RN(rd) | RS(rn) | RM(rm));
+ m_buffer.putInt(toARMWord(cc) | MUL | SetConditionalCodes | RN(rd) | RS(rn) | RM(rm));
}
void mull_r(int rdhi, int rdlo, int rn, int rm, Condition cc = AL)
@@ -477,22 +484,22 @@
void ldr_imm(int rd, ARMWord imm, Condition cc = AL)
{
- m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm, true);
+ m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm, true);
}
void ldr_un_imm(int rd, ARMWord imm, Condition cc = AL)
{
- m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm);
+ m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm);
}
void dtr_u(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | transferType | DT_UP, rd, rb, op2);
+ emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
}
void dtr_ur(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | transferType | DT_UP | OP2_OFSREG, rd, rb, rm);
+ emitInstruction(toARMWord(cc) | transferType | DataTransferUp | Op2IsRegisterArgument, rd, rb, rm);
}
void dtr_d(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
@@ -502,17 +509,17 @@
void dtr_dr(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | transferType | OP2_OFSREG, rd, rb, rm);
+ emitInstruction(toARMWord(cc) | transferType | Op2IsRegisterArgument, rd, rb, rm);
}
void dtrh_u(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | transferType | DT_UP, rd, rb, op2);
+ emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
}
void dtrh_ur(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
{
- emitInstruction(toARMWord(cc) | transferType | DT_UP, rd, rn, rm);
+ emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rn, rm);
}
void dtrh_d(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
@@ -529,7 +536,7 @@
{
ASSERT(op2 <= 0xff && rd <= 15);
/* Only d0-d15 and s0, s2, s4 ... s30 are supported. */
- m_buffer.putInt(toARMWord(cc) | DT_UP | type | (rd << 12) | RN(rb) | op2);
+ m_buffer.putInt(toARMWord(cc) | DataTransferUp | type | (rd << 12) | RN(rb) | op2);
}
void fdtr_d(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
@@ -542,13 +549,13 @@
void push_r(int reg, Condition cc = AL)
{
ASSERT(ARMWord(reg) <= 0xf);
- m_buffer.putInt(toARMWord(cc) | StoreUint32 | DT_WB | RN(ARMRegisters::sp) | RD(reg) | 0x4);
+ m_buffer.putInt(toARMWord(cc) | StoreUint32 | DataTransferWriteBack | RN(ARMRegisters::sp) | RD(reg) | 0x4);
}
void pop_r(int reg, Condition cc = AL)
{
ASSERT(ARMWord(reg) <= 0xf);
- m_buffer.putInt(toARMWord(cc) | (LoadUint32 ^ DT_PRE) | DT_UP | RN(ARMRegisters::sp) | RD(reg) | 0x4);
+ m_buffer.putInt(toARMWord(cc) | (LoadUint32 ^ DataTransferPostUpdate) | DataTransferUp | RN(ARMRegisters::sp) | RD(reg) | 0x4);
}
inline void poke_r(int reg, Condition cc = AL)
@@ -773,28 +780,28 @@
static ARMWord* getLdrImmAddress(ARMWord* insn)
{
// Check for call
- if ((*insn & 0x0f7f0000) != 0x051f0000) {
+ if ((*insn & LdrPcImmediateInstructionMask) != LdrPcImmediateInstruction) {
// Must be BLX
- ASSERT((*insn & 0x012fff30) == 0x012fff30);
+ ASSERT((*insn & BlxInstructionMask) == BlxInstruction);
insn--;
}
// Must be an ldr ..., [pc +/- imm]
- ASSERT((*insn & 0x0f7f0000) == 0x051f0000);
+ ASSERT((*insn & LdrPcImmediateInstructionMask) == LdrPcImmediateInstruction);
- ARMWord addr = reinterpret_cast<ARMWord>(insn) + DefaultPrefetching * sizeof(ARMWord);
- if (*insn & DT_UP)
- return reinterpret_cast<ARMWord*>(addr + (*insn & SDT_OFFSET_MASK));
- return reinterpret_cast<ARMWord*>(addr - (*insn & SDT_OFFSET_MASK));
+ ARMWord addr = reinterpret_cast<ARMWord>(insn) + DefaultPrefetchOffset * sizeof(ARMWord);
+ if (*insn & DataTransferUp)
+ return reinterpret_cast<ARMWord*>(addr + (*insn & DataTransferOffsetMask));
+ return reinterpret_cast<ARMWord*>(addr - (*insn & DataTransferOffsetMask));
}
static ARMWord* getLdrImmAddressOnPool(ARMWord* insn, uint32_t* constPool)
{
// Must be an ldr ..., [pc +/- imm]
- ASSERT((*insn & 0x0f7f0000) == 0x051f0000);
+ ASSERT((*insn & LdrPcImmediateInstructionMask) == LdrPcImmediateInstruction);
if (*insn & 0x1)
- return reinterpret_cast<ARMWord*>(constPool + ((*insn & SDT_OFFSET_MASK) >> 1));
+ return reinterpret_cast<ARMWord*>(constPool + ((*insn & DataTransferOffsetMask) >> 1));
return getLdrImmAddress(insn);
}
@@ -808,8 +815,8 @@
static ARMWord patchConstantPoolLoad(ARMWord load, ARMWord value)
{
value = (value << 1) + 1;
- ASSERT(!(value & ~0xfff));
- return (load & ~0xfff) | value;
+ ASSERT(!(value & ~DataTransferOffsetMask));
+ return (load & ~DataTransferOffsetMask) | value;
}
static void patchConstantPoolLoad(void* loadAddr, void* constPoolAddr);
@@ -839,7 +846,7 @@
ARMWord* instruction = reinterpret_cast<ARMWord*>(where);
ASSERT((*instruction & 0x0f700000) == LoadUint32);
if (value >= 0)
- *instruction = (*instruction & 0xff7ff000) | DT_UP | value;
+ *instruction = (*instruction & 0xff7ff000) | DataTransferUp | value;
else
*instruction = (*instruction & 0xff7ff000) | -value;
cacheFlush(instruction, sizeof(ARMWord));
@@ -891,13 +898,13 @@
static void replaceWithJump(void* instructionStart, void* to)
{
ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart) - 1;
- intptr_t difference = reinterpret_cast<intptr_t>(to) - (reinterpret_cast<intptr_t>(instruction) + DefaultPrefetching * sizeof(ARMWord));
+ intptr_t difference = reinterpret_cast<intptr_t>(to) - (reinterpret_cast<intptr_t>(instruction) + DefaultPrefetchOffset * sizeof(ARMWord));
if (!(difference & 1)) {
difference >>= 2;
- if ((difference <= BOFFSET_MAX && difference >= BOFFSET_MIN)) {
+ if ((difference <= MaximumBranchOffsetDistance && difference >= MinimumBranchOffsetDistance)) {
// Direct branch.
- instruction[0] = B | AL | (difference & BRANCH_MASK);
+ instruction[0] = B | AL | (difference & BranchOffsetMask);
cacheFlush(instruction, sizeof(ARMWord));
return;
}
@@ -919,9 +926,9 @@
ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
cacheFlush(instruction, sizeof(ARMWord));
- ASSERT((*instruction & 0x0ff00000) == 0x02800000 || (*instruction & 0x0ff00000) == 0x05900000);
- if ((*instruction & 0x0ff00000) == 0x02800000) {
- *instruction = (*instruction & 0xf00fffff) | 0x05900000;
+ ASSERT((*instruction & LdrOrAddInstructionMask) == AddImmediateInstruction || (*instruction & LdrOrAddInstructionMask) == LdrImmediateInstruction);
+ if ((*instruction & LdrOrAddInstructionMask) == AddImmediateInstruction) {
+ *instruction = (*instruction & ~LdrOrAddInstructionMask) | LdrImmediateInstruction;
cacheFlush(instruction, sizeof(ARMWord));
}
}
@@ -931,9 +938,9 @@
ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
cacheFlush(instruction, sizeof(ARMWord));
- ASSERT((*instruction & 0x0ff00000) == 0x02800000 || (*instruction & 0x0ff00000) == 0x05900000);
- if ((*instruction & 0x0ff00000) == 0x05900000) {
- *instruction = (*instruction & 0xf00fffff) | 0x02800000;
+ ASSERT((*instruction & LdrOrAddInstructionMask) == AddImmediateInstruction || (*instruction & LdrOrAddInstructionMask) == LdrImmediateInstruction);
+ if ((*instruction & LdrOrAddInstructionMask) == LdrImmediateInstruction) {
+ *instruction = (*instruction & ~LdrOrAddInstructionMask) | AddImmediateInstruction;
cacheFlush(instruction, sizeof(ARMWord));
}
}
@@ -965,13 +972,13 @@
static ARMWord getOp2Byte(ARMWord imm)
{
ASSERT(imm <= 0xff);
- return OP2_IMM | imm;
+ return Op2Immediate | imm;
}
static ARMWord getOp2Half(ARMWord imm)
{
ASSERT(imm <= 0xff);
- return OP2_IMM_HALF | (imm & 0x0f) | ((imm & 0xf0) << 4);
+ return ImmediateForHalfWordTransfer | (imm & 0x0f) | ((imm & 0xf0) << 4);
}
#if WTF_ARM_ARCH_AT_LEAST(7)
@@ -979,7 +986,7 @@
{
if (imm <= 0xffff)
return (imm & 0xf000) << 4 | (imm & 0xfff);
- return INVALID_IMM;
+ return InvalidImmediate;
}
#endif
ARMWord getImm(ARMWord imm, int tmpReg, bool invert = false);
@@ -1000,8 +1007,8 @@
static ARMWord placeConstantPoolBarrier(int offset)
{
offset = (offset - sizeof(ARMWord)) >> 2;
- ASSERT((offset <= BOFFSET_MAX && offset >= BOFFSET_MIN));
- return AL | B | (offset & BRANCH_MASK);
+ ASSERT((offset <= MaximumBranchOffsetDistance && offset >= MinimumBranchOffsetDistance));
+ return AL | B | (offset & BranchOffsetMask);
}
#if OS(LINUX) && COMPILER(RVCT)
@@ -1067,7 +1074,7 @@
static ARMWord getConditionalField(ARMWord i)
{
- return i & 0xf0000000;
+ return i & ConditionalFieldMask;
}
static ARMWord toARMWord(Condition cc)
